{@IEEEtranBSTCTL{bstctl:etal,
  CTLuse_forced_etal = {no},
  CTLmax_names_forced_etal = {3},
}

@IEEEtranBSTCTL{bstctl:nodash,
  CTLdash_repeated_names = {no},
}

@IEEEtranBSTCTL{bstctl:simpurl,
  CTLname_url_prefix = {Available: },
}




@INPROCEEDINGS{islped11,
  author={Swaminathan, K. and Kultursay, E. and Saripalli, V. and Narayanan, V. and Kandemir, M.T. and Datta, S.}, 
  booktitle={ISLPED}, 
  title={Improving energy efficiency of multi-threaded applications using heterogeneous {CMOS-TFET} multicores}, 
  year={2011}
}


@inproceedings{codes12,
 author = {Kultursay, E. and Swaminathan, K. and Saripalli, V. and Narayanan, V. and Kandemir, M.T. and Datta, S.},
 title = {Performance enhancement under power constraints using heterogeneous {CMOS-TFET} multicores},
 booktitle = {CODES},
 year = {2012}
} 

@INPROCEEDINGS{steepslope, 
  author={Lu, Z. and others}, 
  booktitle={IEDM}, 
  title={Realizing super-steep subthreshold slope with conventional FDSOI CMOS at low-bias voltages}, 
  year={Dec.} 
}


@INPROCEEDINGS{sram8t,
  author={Chang, L. and others}, 
  booktitle={VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on}, 
  title={Stable {SRAM} cell design for the 32 nm node and beyond}, 
  year={June} 
}

@inproceedings{corefusion,
 author = {Ipek, E. and Kirman, M.  and Kirman, N. and Martinez, J. F.},
 title = {Core fusion: accommodating software diversity in chip multiprocessors},
 booktitle = {Proceedings of the 34th annual international symposium on Computer architecture},
 year = {2007}
} 

@ARTICLE{asymmetric, 
  author={Kumar, R. and Tullsen, D.M. and Jouppi, N.P. and Ranganathan, P.}, 
  journal={Computer}, 
  title={Heterogeneous chip multiprocessors}, 
  year={Nov.}
}

%TFET papers

@inproceedings{mookerjea,
  author={S. Mookerjea and others},
  title={{Experimental Demonstration of 100nm Channel Length {In0.53Ga0.47As}-based Vertical Inter-band Tunnel Field Effect Transistors ({TFETs}) for Ultra Low-Power Logic and {SRAM} Applications}},
  booktitle={IEDM},
  year={2009}
}



@ARTICLE{seabaugh, 
  author={Seabaugh, A. C. and Zhang, Q. }, 
  journal={Proceedings of the IEEE}, 
  title={Low-Voltage Tunnel Transistors for Beyond CMOS Logic}, 
  year={Dec.}
}



@article{salahuddin,
  author = {Salahuddin, S. and Datta, S. },
  title = {Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices},
  journal = {Nano Letters},
  year = {2008}
}


@inproceedings{taylor-dac2012,
 author = {Taylor, M. B.},
 title = {Is dark silicon useful?: {H}arnessing the four horsemen of the coming dark silicon'apocalypse},
 booktitle = {DAC},
 year = {2012},
} 

@inproceedings{dac11,
  author = { Saripalli, V. and others},
  title = {{An Energy-Efficient Heterogeneous {CMP} based on Hybrid {TFET-CMOS} cores}},
  booktitle ={DAC},
  year = {2011}
}


@inproceedings{slack,
 author = {Fields, B. and Bod\'{\i}k, R. and Hill, M. D.},
 title = {Slack: maximizing performance under technological constraints},
 booktitle = {ISCA},
 series = {ISCA '02},
 year = {2002}
}


@inproceedings{morphcore,
 author = {Khubaib and M. Aater Suleman and Milad Hashemi and Chris Wilkerson and Yale N. Patt},
 title = {MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP},
 booktitle = {MICRO},
 year = {2012}
} 

@ARTICLE{NTC-UMich,
author={Dreslinski, R.G. and Michael Wieckowski and David Blaauw and Dennis Sylvester and Trevor Mudge},
journal={Proceedings of the IEEE},
title={{Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits}},
year={2010}
}

@inproceedings{aergia,
    author = {Das, R. and others},
    title = {Aergia: Exploiting Packet Latency Slack in On-Chip Networks},
    booktitle ={ISCA},
    year = {2010}
}

@inproceedings{asit-sttram,
 author = {Mishra, A. K. and Dong, X. and Sun, G. and Xie, Y. and Vijaykrishnan, N. and Das, C. R.},
 title = {Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs},
 booktitle = {ISCA},
 series = {ISCA '11},
 year = {2011}
} 


@INPROCEEDINGS{iedm11, 
author={Mohata, D.K. and others}, 
booktitle={IEDM}, 
title={Demonstration of {MOSFET-like on-current performance in arsenide/antimonide tunnel FETs} with staggered hetero-junctions for 300mV logic applications}, 
year={2011}
}

@INPROCEEDINGS{iedm09, 
author={Mookerjea, S. and others}, 
booktitle={IEDM}, 
title={{Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications}}, 
year={2009}
}


@misc{intel-gargini,
      title  = "{Intel's Gargini sees tunnel FET as transistor option}",
      author = "Peter Clarke",
      booktitle = "EETimes",
      year   = "2011"
    }


@misc{arm-muller,
      title  = "{ARM CTO warns of Dark Silicon}",
      author = "John Donovan",
      booktitle = "EETimes",
      year   = "2010"
    }

@inproceedings{micro03,
 author = {Kumar, R. and Farkas, K.I. and Jouppi, N.P. and Ranganathan, P. },
 title = {Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction},
 booktitle = {MICRO},
 series = {MICRO 36},
 year = {2003}
}

// Asymmetric CMPs
@inproceedings{isca04,
 author = {Kumar, R. and Tullsen, D. and Ranganathan, P. and Jouppi, N. and Farkas, K},
 title = {Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance},
 booktitle = {ISCA},
 year = {2004}
}

@INPROCEEDINGS{Proactivetemp,
 author={Coskun, A.K and others},
 title={Proactive Temperature Management in MPSoCs},
 booktitle={ISLPED}, 
 year={2011}
}

@article{prometheus,
 author = {Sharifi, S. and others},
 title = {PROMETHEUS: A Proactive Method for Thermal Management of Heterogeneous {MPSoCs}},
 journal = {TCAD},
 year = {2013}
}


@INPROCEEDINGS{ekman-icpp03, 
author={Ekman, M. and Stenstrom, P.}, 
booktitle={Parallel Processing, 2003. Proceedings. 2003 International Conference on}, 
title={Performance and power impact of issue-width in chip-multiprocessor cores}, 
year={2003}
}


@INPROCEEDINGS{vlsit-dhiraj, 
author={Mohata, D.K. and others}, 
booktitle={VLSI Technology (VLSIT)}, 
title={Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio}, 
year={2012}
}

@INPROCEEDINGS{avci-vlsit, 
author={Avci, U.E. and others}, 
booktitle={VLSI Technology (VLSIT)}, 
title={Understanding the feasibility of scaled III-V TFET for logic by bridging atomistic simulations and experimental results}, 
year={2012}
}


@ARTICLE{vinay-jetcas11, 
author={Saripalli, V. and others}, 
journal={Emerging and Selected Topics in Circuits and Systems, IEEE Journal on}, 
title={Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors}, 
year={2011}
}


@ARTICLE{millercap, 
author={Mookerjea, S. and others}, 
journal={Electron Device Letters, IEEE}, 
title={On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors}, 
year={2009}
}



@ARTICLE{iedm12, 
author={Liu, L. and others}, 
journal={Electron Devices, IEEE Trans.}, 
title={Scaling Length Theory of Double-Gate Interband Tunnel Field-Effect Transistors}, 
year={2012}
}


@INPROCEEDINGS{mcpat, 
author={Li, S. and others}, 
booktitle={MICRO}, 
title={{McPAT}: An integrated power, area, and timing modeling framework for multicore and manycore architectures}, 
year={2009}
}


@INPROCEEDINGS{hotspot,
    author = {Huang, W. and others},
    title = {Accurate Pre-{RTL} Temperature-Aware Design Using a Parameterized, Geometric Thermal Model},
    booktitle = {ISSCC},
    year = {2008}
}



@misc{tcad-sentaurus,
      title  = "{TCAD Sentaurus Device Manual}",
      author = "",
      booktitle = "Synopsis",
      year   = "2010"
   }


@inproceedings{ parsec,
  author = {Bienia, C. and Li, K},
  title = {{PARSEC 2.0}: A New Benchmark Suite for Chip-Multiprocessors},
  booktitle = {Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation},
  year = {2009}}
}


@article{gems,
 author = {Martin, M.K. and others},
 title = {Multifacet's general execution-driven multiprocessor simulator ({GEMS}) toolset},
 journal = {SIGARCH Comput. Archit. News},
 year = {2005} 
}


@INPROCEEDINGS{huichu-iedm12, 
author={Liu, H. and others}, 
booktitle={IEDM}, 
title={Technology assessment of {Si} and {III-V} {FinFETs} and {III-V} tunnel {FETs} from soft error rate perspective}, 
year={2012}
}

@inproceedings{conservation-cores,
 author = {Venkatesh, G. and others},
 title = {Conservation cores: reducing the energy of mature computations},
 booktitle = {ASPLOS},
 year = {2010}
}
 
@ARTICLE{king-end-cmos-scaling,
author={Skotnicki, T. and others},
journal={IEEE Circuits and Devices Magazine},
title={{The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance}},
year={2005}
}


@INPROCEEDINGS{isqed05, 
author={Link, G.M. others}, 
booktitle={Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on}, 
title={Thermal trends in emerging technologies}, 
year={2006}
}


@inproceedings{slack-tullsen,
 author = {Seng, John S. and others},
 title = {Reducing power with dynamic critical path information},
 booktitle = {MICRO},
 series = {MICRO 34},
 year = {2001}
}

@INPROCEEDINGS{slack-zhang, 
author={Zhang, W. and others}, 
booktitle={Design, Automation and Test in Europe Conference and Exhibition, 2003}, 
title={Compiler support for reducing leakage energy consumption}, 
year={2003}
}


@inproceedings{isca11-darksilicon,
   author={Hadi Esmaeilzadeh and Emily Blem and Renee St. Amant and Karthikeyan Sankaralingam and Doug Burger},
   title={{Dark Silicon and the End of Multicore Scaling}},
   booktitle="{Proceedings of the 38th International Symposium on Computer Architecture (ISCA)}",
   year={2011}
 }

@inproceedings{venkatesh2010conservation,
author = {Venkatesh, Ganesh and Sampson, Jack and Goulding, Nathan and Garcia, Saturnino and Bryksin, Vladyslav and Lugo-Martinez, Jose and Swanson, Steven and Taylor, Michael Bedford},
 title = {Conservation cores: reducing the energy of mature computations},
 booktitle = {Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems},
 series = {ASPLOS XV},
 year = {2010},
 isbn = {978-1-60558-839-1},
 location = {Pittsburgh, Pennsylvania, USA},
 pages = {205--218},
 numpages = {14},
 url = {http://doi.acm.org/10.1145/1736020.1736044},
 doi = {10.1145/1736020.1736044},
 acmid = {1736044},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {conservation core, heterogeneous many-core, patching, utilization wall},
} 



@ARTICLE{kmeans, 
author={Lloyd, S.}, 
journal={Information Theory, IEEE Transactions on}, 
title={Least squares quantization in PCM}, 
year={1982}}


@misc{digitalversus-samsung,
      title  = "{Samsung Galaxy S II: Clock Rate and Temperature Differences}",
      author = "Vincent Alzieu ",
      booktitle = "Digital Versus",
      year   = "2012"
    }

@misc{pcworld-laptop,
      title  = "{Free Utility Core Temp Tells You If Your CPU Is Overheating}",
      author = "Erez Zukerman",
      booktitle = "PCWorld",
      year   = "2011"
    }






@ARTICLE{thermal-dvfs-asu, 
author={Hanumaiah, V. and Vrudhula, S.}, 
journal={Computers, IEEE Transactions on}, 
title={Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors}, 
year={2012}, 
volume={61}, 
number={10}, 
pages={1484-1494}, 
doi={10.1109/TC.2011.156}, 
ISSN={0018-9340},
}


@INPROCEEDINGS{ionescu-3D, 
author={Fernandez-Bolanos, M. and Ionescu, A.M.}, 
booktitle={3D Systems Integration Conference (3DIC), 2010 IEEE International}, 
title={{3D} heterogeneous integration for novel functionality}, 
year={2010}, 
pages={1-19}, 
doi={10.1109/3DIC.2010.5751423}
}

@INPROCEEDINGS{ionescu-nems, 
author={Ionescu, A.-M. and De Michielis, L. and Dagtekin, N. and Salvatore, G. and Ji Cao and Rusu, A. and Bartsch, S.}, 
booktitle={Electron Devices Meeting (IEDM), 2011 IEEE International}, 
title={Ultra low power: Emerging devices and their benefits for integrated circuits}, 
year={2011}, 
pages={16.1.1-16.1.4}, 
doi={10.1109/IEDM.2011.6131563}, 
ISSN={0163-1918},
}


@INPROCEEDINGS{tullsen-3D, 
author={Homayoun, H. and Kontorinis, V. and Shayan, A. and Ta-Wei Lin and Tullsen, D.M.}, 
booktitle={High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on}, 
title={Dynamically heterogeneous cores through 3D resource pooling}, 
year={2012}, 
pages={1-12}, 
doi={10.1109/HPCA.2012.6169037}, 
ISSN={1530-0897},}


@ARTICLE{ieeemicro-sprinting, 
author={Raghavan, A. and Emurian, L. and Lei Shao and Papaefthymiou, M. and Pipe, K.P. and Wenisch, T.F. and Martin, M.M.K.}, 
journal={Micro, IEEE}, 
title={Utilizing Dark Silicon to Save Energy with Computational Sprinting}, 
year={2013}, 
volume={33}, 
number={5}, 
pages={20-28}, 
doi={10.1109/MM.2013.76}, 
ISSN={0272-1732},
}

ARTICLE{ieeemicro-tfet, 
author={Swaminathan, K. and Kultursay, E. and Saripalli, V. and Narayanan, V. and Kandemir, M.T. and Datta, S.}, 
journal={Micro, IEEE}, 
title={Steep-Slope Devices: From Dark to Dim Silicon}, 
year={2013}, 
volume={33}, 
number={5}, 
pages={50-59}, 
keywords={CMOS integrated circuits;microprocessor chips;multiprocessing systems;power aware computing;CMOS technology;device-level heterogeneous multicores;energy efficiency;resource-management schemes;sequential applications;smart resource management;steep-slope devices;subthreshold characteristics;CMOS integrated circuits;Dynamic scheduling;Low voltage;Multicore processing;Performance evaluation;Program processors;Semiconductor device manufacture;Silicon;CMOS-TFET heterogeneous architectures;DVFS;dark silicon;dim silicon;dynamic voltage and frequency scaling;power partitioning;steep-slope devices;thread migration}, 
doi={10.1109/MM.2013.75}, 
ISSN={0272-1732},
}

@ARTICLE{Dennard1974, 
author={Dennard, R.H. and Gaensslen, F.H. and Rideout, V.L. and Bassous, E. and LeBlanc, A.R.}, 
journal={Solid-State Circuits, IEEE Journal of}, 
title={Design of ion-implanted MOSFET's with very small physical dimensions}, 
year={1974}, 
volume={9}, 
number={5}, 
pages={256-268}, 
keywords={Digital integrated circuits;Field effect transistors;Ion implantation;Semiconductor device manufacture;Switching circuits;digital integrated circuits;field effect transistors;ion implantation;semiconductor device manufacture;switching circuits;Digital integrated circuits;Doping profiles;Fabrication;Ion implantation;Length measurement;MOSFET circuits;Predictive models;Semiconductor process modeling;Switching circuits;Threshold voltage}, 
doi={10.1109/JSSC.1974.1050511}, 
ISSN={0018-9200},}

@inproceedings{hhlee-3D-dvfs,
 author = {Choi, Hong Jun and Park, Young Jin and Lee, Hsien-Hsin and Kim, Cheol Hong},
 title = {Adaptive Dynamic Frequency Scaling for Thermal-aware 3D Multi-core Processors},
 booktitle = {Proceedings of the 12th International Conference on Computational Science and Its Applications - Volume Part IV},
 series = {ICCSA'12},
 year = {2012},
 isbn = {978-3-642-31127-7},
 location = {Salvador de Bahia, Brazil},
 pages = {602--612},
 numpages = {11},
 url = {http://dx.doi.org/10.1007/978-3-642-31128-4_44},
 doi = {10.1007/978-3-642-31128-4_44},
 acmid = {2346389},
 publisher = {Springer-Verlag},
 address = {Berlin, Heidelberg},
 keywords = {3D integration technology, dynamic frequency scaling, multi-core processor, processor architecture, thermal management},
}

@INPROCEEDINGS{yibo-yield-iccad, 
author={Yibo Chen and Dimin Niu and Yuan Xie and Chakrabarty, K}, 
booktitle={Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on}, 
title={Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis}, 
year={2010}, 
pages={471-476}, 
doi={10.1109/ICCAD.2010.5653753}, 
ISSN={1092-3152},} 


@INPROCEEDINGS{microfluidic-cooling, 
author={Yue Zhang and Dembla, A. and Joshi, Y. and Bakir, M.S.}, 
booktitle={Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd}, 
title={3D stacked microfluidic cooling for high-performance 3D ICs}, 
year={2012}, 
pages={1644-1650}, 
doi={10.1109/ECTC.2012.6249058}, 
ISSN={0569-5503},}

@ARTICLE{ieeemicro-llano, 
author={Branover, A. and Foley, D. and Steinman, M.}, 
journal={Micro, IEEE}, 
title={AMD Fusion APU: Llano}, 
year={2012}, 
volume={32}, 
number={2}, 
pages={28-37}, 
doi={10.1109/MM.2012.2}, 
ISSN={0272-1732},}

@inproceedings{hotspot3d,
 author = {Meng, Jie and Kawakami, Katsutoshi and Coskun, Ayse K.},
 title = {Optimizing Energy Efficiency of 3-D Multicore Systems with Stacked DRAM Under Power and Thermal Constraints},
 booktitle = {Proceedings of the 49th Annual Design Automation Conference},
 series = {DAC '12},
 year = {2012},
 isbn = {978-1-4503-1199-1},
 location = {San Francisco, California},
 pages = {648--655},
 numpages = {8},
 url = {http://doi.acm.org/10.1145/2228360.2228477},
 doi = {10.1145/2228360.2228477},
 acmid = {2228477},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {3D multicore system, energy efficiency, thermal management},
}

@misc{itrs2011,
      title  = {The International Technology Roadmap for Semiconductors {(ITRS)}},
      author = "ITRS",
      booktitle = "System Drivers",
      year   = "2011"
   }
 
@INPROCEEDINGS{sniper, 
author={Carlson, T.E. and Heirman, W. and Eeckhout, L.}, 
booktitle={High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for}, 
title={Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation}, 
year={2011}, 
pages={1-12}, 
keywords={cache storage;digital simulation;multiprocessing systems;16-core system;8-core SMP machine;Sniper;abstraction level exploration;core larger numbers;core-uncore interactions;cycle-accurate simulation;hardware design space;high-performance computing;interval simulation;multithreaded workloads;on-chip cache memory;one-IPC simulation;parallel multicore simulation;processor architectures;Accuracy;Analytical models;Kernel;Load modeling;Multicore processing;Synchronization;Interval simulation;interval model;multi-core processor;performance modeling},}


@ARTICLE{Lu-tfet-scaling, 
author={Lu Liu and Mohata, D. and Datta, S.}, 
journal={Electron Devices, IEEE Transactions on}, 
title={Scaling Length Theory of Double-Gate Interband Tunnel Field-Effect Transistors}, 
year={2012}, 
volume={59}, 
number={4}, 
pages={902-908}, 
keywords={Green's function methods;insulated gate field effect transistors;tunnel transistors;atomistic nonequilibrium Green function simulation;band-to-band tunneling generation rate;commercial simulator;double-gate interband tunnel field-effect transistor;electrostatic potential profile;electrostatic scaling length;heterojunction TFET;homojunction TFET;physics-based 2D analytical model;scaling length theory;short-channel performance;Analytical models;Electric potential;Electrostatics;Heterojunctions;Logic gates;MOSFETs;Tunneling;Analytical model;drain-induced barrier lowering (DIBL);drain-induced barrier thinning (DIBT);scalability;short-channel effect;tunnel field-effect transistor (TFET)}, 
doi={10.1109/TED.2012.2183875}, 
ISSN={0018-9383},}


@INPROCEEDINGS{emma-3d, 
author={Emma, P. and Buyuktosunoglu, A. and Healy, M. and Kailas, K. and Puente, V. and Yu, R. and Hartstein, A. and Bose, P. and Moreno, J.}, 
booktitle={High Performance Computer Architecture (HPCA) Industry Session, 2014 IEEE 20th International Symposium on}, 
title={{3D} stacking of High Performance Processors}, 
year={2014}, 
pages={1-12}, 
ISSN={1530-0897},}

@INPROCEEDINGS{tfet-sram, 
author={Saripalli, V. and Datta, S. and Narayanan, V. and Kulkarni, J.P.}, 
booktitle={Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on}, 
title={Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design}, 
year={2011}, 
pages={45-52}, 
keywords={CMOS integrated circuits;SRAM chips;field effect transistors;low-power electronics;power aware computing;trigger circuits;Schmitt-Trigger feedback mechanism;low supply voltage applications;uni-directional conduction;variation-tolerant ultra low-power heterojunction tunnel FET SRAM design;voltage 124 mV;CMOS integrated circuits;FinFETs;Logic gates;Noise;Random access memory;Silicon}, 
doi={10.1109/NANOARCH.2011.5941482},}

@INPROCEEDINGS{tfet-intel, 
author={Dewey, G. and Chu-Kung, B. and Boardman, J. and Fastenau, J. M. and Kavalieros, J. and Kotlyar, R. and Liu, W. K. and Lubyshev, D. and Metz, M. and Mukherjee, N. and Oakey, P. and Pillarisetty, R. and Radosavljevic, M. and Then, H. W. and Chau, R.}, 
booktitle={Electron Devices Meeting (IEDM), 2011 IEEE International}, 
title={Fabrication, characterization, and physics of {III-V} heterojunction tunneling Field Effect Transistors {(H-TFET)} for steep sub-threshold swing}, 
year={2011}, 
pages={33.6.1-33.6.4}, 
keywords={III-V semiconductors;field effect transistors;semiconductor doping;semiconductor heterojunctions;tunnel transistors;H-TFET;III-V heterojunction tunneling field effect transistors;drain current;drive current;electrical oxide thickness scaling;heterojunction engineering;source doping;source-to-channel tunnel barrier height;steep subthreshold swing;thin gate oxide;Doping;Gate leakage;HEMTs;Heterojunctions;Indium gallium arsenide;Logic gates}, 
doi={10.1109/IEDM.2011.6131666}, 
ISSN={0163-1918},}


@inproceedings{reetu-3d-cost,
 author = {Wu, Xiaoxia and Sun, Guangyu and Dong, Xiangyu and Das, Reetuparna and Xie, Yuan and Das, Chita and Li, Jian},
 title = {Cost-driven 3D Integration with Interconnect Layers},
 booktitle = {Proceedings of the 47th Design Automation Conference},
 series = {DAC '10},
 year = {2010},
 isbn = {978-1-4503-0002-5},
 location = {Anaheim, California},
 pages = {150--155},
 numpages = {6},
 url = {http://doi.acm.org/10.1145/1837274.1837313},
 doi = {10.1145/1837274.1837313},
 acmid = {1837313},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {interconnect service layer, network-on-chip, three-dimensional integrated circuit},
} 
